



















                                     PCLA

                              An IBM P.C. Based
                                Logic Analyzer





                                 Release 1.0

                              Revised 27-Mar-00










                         Dunfield Development Systems
                         ----------------------------
                            High quality tools for
                             Embedded Development
                                at low prices.

                           http://www.dunfield.com


                      Copyright 2000-2005 Dave Dunfield
                             All rights reserved



                              PC Logic Analyzer

                              TABLE OF CONTENTS


                                                                        Page

    1. INTRODUCTION                                                        1

       1.1 Hardware Requirements                                           1

    2. INTERFACING TO THE TARGET SYSTEM                                    2

       2.1 Connection Issues                                               2
       2.2 Pin Connections                                                 2
       2.3 Protective Circuitry                                            3
       2.4 Physical Considerations                                         3

    3. RUNNING PCLA                                                        4

       3.1 Command Line Options                                            4

    4. USING PCLA                                                          6

       4.1 Monitor mode                                                    6
       4.2 Reviewing Data                                                  9
       4.3 Previewing Data                                                10

    5. OPERATIONAL TIPS                                                   12

       5.1 Aliasing                                                       12
       5.2 Slowing it down                                                13

    6. File Formats                                                       14


    7. APPENDIX A - Modifying older Parallel Ports                        15


    8. APPENDIX B - A Programmable Clock Generator                        16


    9. APPENDIX C - Making a clean boot disk                              18

   PC Logic Analyzer                                                Page: 1


   1. INTRODUCTION

         PCLA is a simple PC based Logic Analyzer which uses  the  parallel
      port as an input device to monitor and record the activity of  up  to
      13 TTL level logic  signals  in  real  time.  PCLA  uses  a  standard
      bidirectional PC/LPT port,  and no additional  hardware  is  required
      (you may want to provide some protection for  the  parallel  port  as
      discussed later in this document).

         PCLA is **NOT** a high-speed logic analyzer.  The speed  at  which
      the PC can poll the parallel port is limited, making PCLA a low speed
      device.  For most PC's of 486/33 or faster,  PCLA will have a maximum
      sampling rate of between 375  and  500  Khz  (2.6-2.0us/sample).  For
      faster PC's the speed is limited by the ability  of  the  chipset  to
      perform I/O to the LPT port more than it is by CPU speed.

      1.1 Hardware Requirements

            PCLA requires a 486/33 of faster PC/AT compatible  running  DOS
         3.0 or higher. A slower PC will work, however you may experience a
         reduced sampling rate.

            PCLA also requires a bidirectional parallel port. Most ports on
         modern PC's have  bidirectional  capability,  however  some  older
         ports are not.  If the  older  port  is  on  a  ISA  card  and  is
         constructed from discrete TTL logic,  you may be able to  make  it
         into a bidirectional port with little difficulty (See Appendix A).
         A non-bidirectional port can be used,  however you will be limited
         to monitoring the 5 control lines (A-E).

            Finally,  you will need a cable to connect  the  parallel  port
         inputs to your target system.  See the following section for  more
         information and ideas.
   PC Logic Analyzer                                                Page: 2


   2. INTERFACING TO THE TARGET SYSTEM

         In the simplest form, you could simply make a cable which connects
      the required parallel port signals to the test points on  the  target
      system that you wish to monitor,  however there are some issues  that
      you should be aware of:

      2.1 Connection Issues

            The signals transmitted and received on the  PC  parallel  port
         are TTL level signals.  These have a range of 0v  (logic  0/system
         ground) to +5V (logic high). A logic low should be less than 0.8v,
         while a logic high should be greater than 2.4v.  Connection of the
         parallel port signals to any voltages outside of this  range  will
         damage the parallel port.

            Pins 2-9 are the parallel port DATA pins,  which  are  normally
         configured by the PC as OUTPUTS.  This means that if  you  connect
         these pins to your target system,  they will be sending power into
         the target until you run PCLA.  This has two major problems, 1) it
         may cause undesired operation of the target,  and 2)  signals from
         the target will be "fighting" with the signals from the PC,  which
         may stress the parallel port and/or target hardware and  cause  it
         to fail.

            For this reason, it is strongly advised that you do not connect
         the target system to the PC parallel port after turning the PC on,
         until you have run PCLA at least once.

      2.2 Pin Connections

         PCLA reads it's data from the following pins of the parallel port:

           Pin Signal  Pin Signal
           -----------------------------
            2 -Data 0  15 -Data A
            3 -Data 1  13 -Data B
            4 -Data 2  12 -Data C
            5 -Data 3  10 -Data D
            6 -Data 4  11 -Data E
            7 -Data 5
            8 -Data 6
            9 -Data 7   18-25 -Ground
   PC Logic Analyzer                                                Page: 3


      2.3 Protective Circuitry

            You should also be mindful of the possibility of damage to  the
         PC parallel port.  As noted above,  the PC port can be damaged  by
         excessive stress from conflicting outputs,  however it can also be
         damaged by static discharge, or by accidental contact with non-TTL
         level voltages in the target system. For this reason, you may want
         to consider adding some protective circuitry to all of the signals
         used on the parallel port.

            The  most  basic  protection  circuit  is  a  current  limiting
         resistor. I have found that a 150 Ohm resistor in series with each
         line works well to prevent excessive current, while still offering
         a low enough resistance that TTL low's will be correctly sensed.

            Further protection can be achieved by using Diodes  on  the  PC
         side of the current limiting resistor to  insure  that  the  input
         voltage does not go above +5v or below 0v  (Ground).  Since  a  5v
         reference is not available on the PC parallel port,  you may  wish
         to use a Zener diode to provide one.  The drawing file PCINPUT.DWG
         contains  a  MICROCAD  format  drawing  of  some   example   input
         protection circuitry.

            It is also worth mentioning that some parallel ports  are  much
         more difficult to replace than others.  If possible,  I  recommend
         using a cheap parallel port Add-in card. If you damage it, you can
         simply replace it with another one.  If on  the  other  hand,  you
         damage the parallel port on your  mainboard,  or  worse,  in  your
         laptop computer, this can be very expensive to fix!.

            My own setup  is  an  add-on  LPT  port  with  150  Ohm  series
         resistors, which I have found to be quite satisfactory.

      2.4 Physical Considerations

            On the matter of physically connecting to the target system,  I
         recommend building a small circuit board which  contains  a  DB-25
         connector for connection to the PC via an "off the shelf" cable, a
         couple of 150 Ohm  "resistor packs"  which will provide 14  series
         resistors (you need 13) in two neat DIP packages,  and a couple of
         DIP headers for connection to the target system.

            I arranged the DIP headers in two groups,  one of 8  pairs  for
         the 0-7 data lines,  and one of 5 pairs for the  A-E  data  lines.
         Ground all pins on one side of the header, and connect the pins on
         the other side through the resistor packs to the DB-25  connector.
         A standard ribbon cable and connector will  fit  the  headers  and
         provide alternating ground and signal wires.

            I used about a 1-foot long ribbon cable,  and  split  it  apart
         about halfway along it's length  (At this point,  I just  cut  the
         ground wires off).  The remaining data signals should be connected
         to miniture  "test point"  clips,  the kind that have a small hook
         that can grab onto a test point pin or device lead.
   PC Logic Analyzer                                                Page: 4


   3. RUNNING PCLA

         PCLA is a very timing intensive program, and for this reason it is
      not recommended that you run it from within windows. Windows does not
      provide the real-time processing  ability  which  PCLA  requires  for
      accurate data sampling.

         If you are using a Windows9x system,  you should use the  "Restart
      computer in MSDOS mode"  option from the SHUTDOWN menu before running
      PCLA.

         If you are using Windows 3.1,  you should exit  back  to  the  DOS
      prompt before running PCLA.

         PCLA will not run under WindowsNT  due  to  it's  requirement  for
      direct access to the parallel port hardware  (which  WinNT  does  not
      allow).

         It should also be noted  that  TSR's,  device  drivers  and  other
      resident  programs  may  perform  background  processing  which  will
      interfere with PCLA's sampling.  If you have such things loaded,  you
      should unload them before using PCLA. It may be desirable to create a
      bootable floppy disk which will enable you to "clean boot" the system
      before running PCLA. See APPENDIX C for more information.

      3.1 Command Line Options

         PCLA supports the following command line options.



         /D - Prevent unused entry detection in preview

               If there are less then 256 preview entries,  PCLA  tries  to
            identify unused ones by using unstandardized  features  of  the
            parallel port hardware.  If you are getting  incorrect  preview
            displays, use this option to disable this.  Unused entries will
            then show simply as all lines at logic 0.

         /O - Revert parallel data lines to outputs on exit

               Normally,  PCLA will configure the parallel port data  lines
            to be inputs,  and will leave the parallel port configured this
            way when it exits. This is generally the most convenient, as it
            prevents any signal conflicts from  occurring  on  these  lines
            once PCLA has been run once.

               If however you need to have the  parallel  port  data  lines
            revert to being outputs after PCLA exits,  you may use the '/O'
            option to accomplish this.
   PC Logic Analyzer                                                Page: 5


         /O* - Revert parallel data lines to outputs and exit immediately.

               This option causes PCLA to configure the parallel data lines
            as outputs,  and terminate immediately.  No  screen  output  is
            produced.  This option is most useful from within "batch" files
            to re-configure the parallel port after a PCLA session.

         /I - Disable interrupts during capture

               When you are capturing data at very  high  rates,  the  time
            taken to service interrupts on the PC can cause sampling  gaps.
            This occurs because the PCLA code is polling the parallel  port
            in a very tight loop, and has to "take time out" to service the
            interrupt.  The  effect  will  be  more  pronounced  on  slower
            machines.

               The  '/I'  option disables  all  interrupts  during  capture
            except for the keyboard interrupt  (which is required in  order
            to abort the capture).  This will prevent  the  sampling  gaps,
            however it also means that the PC time-of-day  clock  will  not
            advance while PCLA is waiting for a trigger, or acquiring data.
            This has  the  effect  that  the  PC's  clock  loses  time.  To
            compensate  for  this,  PCLA  will  automatically  set  the  PC
            time-of-day clock to the time currently indicated by  the  PC's
            real time  (CMOS)  clock chip at the end of every capture cycle
            when this option is used.

         /I* - Disable interrupts during capture but do not reset clock

               This option causes PCLA to disable interrupts during capture
            as  described  above,  but  prevents  it  from  resetting   the
            time-of-day clock.  This should  be  used  if  your  PC  has  a
            non-standard clock chip, or you do not want the clock reset for
            any other reason.

         /M - Force monochrome screens

               PCLA will automatically detect a color adapter, and will use
            more pleasing color screens when one is found. If you happen to
            be using a monochrome monitor with a  color  adapter,  you  may
            need to specify the  '/M'  option to  force  PCLA  to  use  the
            monochrome screen format.

         /W - Display wiring information

               This option causes PCLA to display a small  summary  of  the
            parallel port signal pins, and then terminate.

         I=n - Set default capture interval (microseconds)

               This option sets  the  capture  interval  to  the  specified
            number of microseconds. The capture interval defines the length
            of time which PCLA waits between each  sampling  of  the  input
            data lines during the  "T"rigger and  "A"cquire phases of  data
            capture.
   PC Logic Analyzer                                                Page: 6


         M=n - Set default monitor update interval (milliseconds)

               This option defines the amount  of  time  occurring  between
            each sample in the "monitor" screen.  This time is derived from
            the PC clock tick,  and has a  resolution  of  55  milliseconds
            only.

         P=1-3/address - Set parallel port number/address

               This option specifies the parallel port which will  be  used
            by PCLA.  A value of 1-3 indicates the port LPTn as detected by
            the BIOS.  A value >3 indicates an  absolute  I/O  address  (in
            hexidecimal).  The standard parallel port addresses  are:  3BC,
            378 and 278.

         S=n - Set number of samples

               This options sets the default number of samples  which  will
            be collected during the "A"cquire phase of data capture.

   4. USING PCLA

         When launched,  PCLA starts up in "monitor"  mode,  where it polls
      the parallel port at regular intervals,  and draws a scrolling  graph
      showing the logic levels.  This is  a  low-speed  display,  which  is
      mainly intended to let you see the current state of the logic  inputs
      "at a glance".

      4.1 Monitor mode

            This  "monitor"  mode may also be considered the  main  screen,
         with all  functions  of  PCLA  being  accessed  from  subfunctions
         activated here:


          C)apture - Begin high-speed data capture

               This function causes PCLA to  begin  data  acquisition.  The
            parallel inputs are read at the sampling interval  [See  S)etup
            function],  and compared with the trigger  mask  [See  T)rigger
            function]. This will be repeated until a match occurs (note, if
            all triggers are set to "X - Don't care",  the match will occur
            immediately). The fact that PCLA is waiting for a trigger match
            is indicated by "[T]" in the upper left corner of the display.

               Once a trigger match occurs, PCLA will begin acquiring data.
            The parallel inputs are  read  at  the  sampling  interval  and
            stored in memory.  This will  be  repeated  until  the  defined
            number of samples has been stored  [See S)etup function].  When
            PCLA enters this  "acquire"  phase of the capture process,  the
            "[T]"  in the upper left corner of the screen  will  change  to
            "[A]".

               At any time,  you  may  terminate  the  capture  process  by
            pressing the ESCAPE key.
   PC Logic Analyzer                                                Page: 7


               Once the capture process has completed,  you  may  view  the
            stored  data  with  the  "Review"  function.  The  255  samples
            occurring immediately before the trigger match  may  be  viewed
            with the "Preview" function.

               Note that if the "/I" option is in effect, the PC interrupts
            will be disabled during the capture process (Both [T]rigger and
            [A]cquision).  This causes the PC  time-of-day  clock  to  lose
            time.  In this case,  PCLA will reset the time-of-day clock  to
            the real-time  (CMOS)  clock unless the "/I*" option was given,
            in which case the time-of-day clock will lose time.

         F)ile - Perform File operations

               This function allows you to load or store the captured  data
            and certain configuration parameters to and from  a  flie.  You
            will be prompted for the operation  (Load  or  Save),  and  the
            filename.

               The information saved and loaded from the file is:

           - The configured sampling interval
           - The configured number of samples
           - The configured trigger information
           - The position in the preview buffer
           - The preview data
           - The size of the review data
           - The review data

         M)onitor - Set the monitoring interval rate

               Prompts you with the current monitoring interval  rate,  and
            allows you to  change  it.  The  monitoring  interval  rate  is
            specified in milliseconds,  by is actually measured in "chunks"
            of 55 ms (the PC clock tick interval).

               The monitoring interval rate  defines  how  frequently  PCLA
            will sample the input lines and update the monitor display when
            operating in monitor mode.

         P)review - Preview data before trigger of last capture

               Enters the preview viewer,  and allows you to view  the  255
            samples which occurred immediately  before  the  trigger  match
            occurred on your last C)apture function.

         R)eview - Review acquired data

               Enter the review viewer,  and allows you to view  the  logic
            data that was acquired following the trigger match on your last
            C)apture function.
   PC Logic Analyzer                                                Page: 8


         S)etup - Setup capture process

               Prompts with the number of samples  and  sampling  interval,
            and allows you to change them. The new values will be in effect
            for all subsequent C)apture functions.

               "Number of samples"  defines  how  many  samples  should  be
            acquired and  stored  following  a  trigger  match  before  the
            capture function is over.  A value of zero is a  special  case,
            and indicates 65536 samples,  the highest number that PCLA  can
            store.

               "Sampling Interval"  defines the period of time  (us)  which
            elapses between each sample taken.

               The total time of the acquisition will  be  the  "Number  of
            samples" multiplied by the "Sampling Interval".

         T)rigger - Set capture trigger

               Brings up a menu of the capture trigger.  This has a setting
            for each input line, which can assume one of three states:

               0   - Bit has to be Zero to match trigger
               1   - Bit has to be One  to match trigger
               X   - Don't care - either 0 or 1 will match

               You may press the letter  ('0-7'  or  'A-E')  of an entry to
            toggle it through the three possible states.  Press ENTER  when
            you are done.

               When you activate the  C)apture  function,  PCLA  will  wait
            until all of the input lines  match  their  respective  trigger
            settings before beginning to acquire and store the data.

         F10:Exit - Terminate PCLA

               This causes PCLA to terminate, and return to the DOS prompt.

               If the '/O' option was specified when PCLA was started,  the
            LPT port data lines are reverted to outputs.
   PC Logic Analyzer                                                Page: 9


      4.2 Reviewing Data

            When you activate the R)eview function from monitor mode,  PCLA
         enters the acquired data viewer.  This viewer shows  the  acquired
         data on the screen in a format similar to monitor  mode,  and  you
         may scroll through the data with the following keys:

           Left and Right arrows   - Move back and forth by 1 character
           Up and Down arrows      - Move back and forth by 10 characters
           PgUp and PgDN           - Move back and forth by 75 characters
           Home                    - Position to the start of the data
           End                     - Position to the end of the data

            A marker line between  the  A-E  and  0-7  displays  shows  the
         position of the screen data within the data buffer.  At  the  left
         end of this marker line is a number representing the  position  of
         the leftmost visible data entry.  At  the  rightmost  end  of  the
         marker line is a number representing the position of the rightmost
         visible data entry (Note:  0 is a special case,  and means 65535 -
         the highest entry number which can be recorded).

            Along the marker  lines,  each  position  is  identified  by  a
         specific character, as follows:

            Positions evenly divisible by 10 are marked with a square.
            Positions evenly divisible by 5 are marked with a large circle.
            All other positions are marked with a small circle (dot).

         In addition to moving around and viewing the  acquired  data,  the
         following functions are available in review mode:

         F1:Search - Search for logic pattern

               Prompts with a match qualifier,  which contains an entry for
            each input line which can assume one of three states:

               0   - Bit has to be Zero to match
               1   - Bit has to be One  to match
               X   - Don't care - either 0 or 1 will match

               You may press the letter  ('0-7'  or  'A-E')  of an entry to
            toggle it through the three possible states.  Press ENTER  when
            you are done.

               PCLA will then search forward through the buffer,  beginning
            at the current display position,  until it finds  an  entry  in
            which all of the input lines correspond to the entries  defined
            in the match qualifier.  If such an entry is found, the viewing
            position is moved to that entry.
   PC Logic Analyzer                                                Page: 10


         F2:Search Again - Search for next occurance of logic pattern

               This function begins searching for a  logic  pattern,  using
            the match qualifier from the previous  F1:Search  command,  and
            beginning at the current display position  in  the  buffer  +1.
            This effectivly searches for the next occurance  of  the  logic
            pattern.

         F3:Count - Count state changes

               Prompts with a state qualifier,  which contains an entry for
            each input line which can assume one of two states:

               X - Don't care  - Ignore changes in this line
               * - Do care     - Notice changes in this line

               You may press the letter  ('0-7'  or  'A-E')  of an entry to
            toggle it through the three possible states.  Press ENTER  when
            you are done.

               PCLA will then scan from the current position to the end  of
            the buffer, and count how many times the state of all '*' lines
            changes  (A change on one or more '*'  line constitutes a state
            change). The count of state changes is then displayed.

               To determine the state  changes  within  a  section  of  the
            buffer which does not reside at the end of the buffer,  perform
            this function at the start of the section, and again at the end
            of the section and subtract the values.

      4.3 Previewing Data

            When you activate the P)review function from monitor mode, PCLA
         enters the preview data viewer.  This viewer shows  the  last  255
         samples which were taken immediately before a  trigger  match  was
         made. You may scroll through the data with the following keys:

           Left and Right arrows   - Move back and forth by 1 character
           Up and Down arrows      - Move back and forth by 10 characters
           Home                    - Position to the start of the data
           End                     - Position to the end of the data
   PC Logic Analyzer                                                Page: 11


            A marker line between  the  A-E  and  0-7  displays  shows  the
         position of the screen data within the data buffer.  At  the  left
         end of this marker line is a number representing the  position  of
         the leftmost visible data entry.  At  the  rightmost  end  of  the
         marker line is a number representing the position of the rightmost
         visible data entry.

            Along the marker  lines,  each  position  is  identified  by  a
         specific character, as follows:

            Positions evenly divisible by 10 are marked with a square.
            Positions evenly divisible by 5 are marked with a large circle.
            All other positions are marked with a small circle (dot).

         NOTE:  Positions shown in preview mode indicate the sample  number
         BEFORE the trigger match,  and therefore get larger  as  you  move
         chronologically backward in time.  Position 0 at the  end  of  the
         buffer indicates the input lines at the moment of trigger match.

         ALSO NOTE,  PCLA does not keep  track  of  the  beginning  of  the
         circular preview data buffer.  It does keep track where the end is
         located,  and will display the last 256 entries in order from  the
         End back.  If the trigger match condition  occurs  LESS  THAN  256
         entries after the capture begins,  the preview buffer will not all
         contain valid data. PCLA tries to identify unused entries by using
         unstandardized features of the data read from  the  port,  however
         this may not work correctly  on  all  PC's.  If  you  are  getting
         no-data indicators in the middle of your preview data,  try  using
         the '/D'  option to disable this detection.  In this case,  unused
         preview entries will show all lines at logic zero (0).

         In addition to moving around and viewing the  acquired  data,  the
         following functions are available in review mode:

         F1:Search - Search for logic pattern

               Prompts with a match qualifier,  which contains an entry for
            each input line which can assume one of three states:

               0   - Bit has to be Zero to match
               1   - Bit has to be One  to match
               X   - Don't care - either 0 or 1 will match

               You may press the letter  ('0-7'  or  'A-E')  of an entry to
            toggle it through the three possible states.  Press ENTER  when
            you are done.

               PCLA will then search backward through the buffer, beginning
            at the current display position,  until it finds  an  entry  in
            which all of the input lines correspond to the entries  defined
            in the match qualifier.  If such an entry is found, the viewing
            position is moved to that entry.
   PC Logic Analyzer                                                Page: 12


         F2:Search Again - Search for next occurance of logic pattern

               This function begins searching for a  logic  pattern,  using
            the match qualifier from the previous  F1:Search  command,  and
            beginning at the current display position  in  the  buffer  -1.
            This effectivly searches for the next occurance  of  the  logic
            pattern.

   5. OPERATIONAL TIPS

      5.1 Aliasing

            When a signal is being sampled,  state changes which  occur  on
         the signal after one sample,  but before  the  next  will  not  be
         visible until that sample has  occurred.  This  causes  an  effect
         called aliasing, in which the waveform that you see is not exactly
         the same as the one being sampled if the sample rate is  close  to
         the state change rate.

            Consider a square wave changing at a  rate  of  3us  per  state
         change.  If we sample this at 2us and at  4us,  we  will  see  the
         following:

           ___---___---___---___---___---___---___ Original Signal
           0..3..3..3..3..3..3..3..3..3..3..3..3..

           ___---____--____--____--____--____--___ 2us sample
           0.2.2.2.2.2.2.2.2.2.2.2.2.2.2.2.2.2.2.2

           ____----________----________----_______ 4us sample
           0...4...4...4...4...4...4...4...4...4..

            Note that when we sampled slightly faster than the state change
         rate, we saw distortion of the waveform, however we did see all of
         the state changes.  This  type  of  aliasing  is  usually  not  to
         detrimental to the non-timing critical logic analysis that PCLA is
         normally used for...

            But! Note what happened when we sampled at a rate  slower  than
         the signal state changes... We completely lost some state changes,
         and in fact,  this case happens to present the signal as  1/2  the
         frequency of the original! This is not good, and clearly shows why
         you need to make sure that you are sampling your signals at  least
         as fast as they can change state.

            Normally, aliasing won't be so regular,  but will occur only at
         points where the target system clock and PC sampling rates are  in
         a specific relationship. This relationship will come and go as the
         two unsynchronized devices  drift.  Be  warned  that  if  you  are
         sampling at rates below the state  change  period  of  the  target
         system, what you are seeing may be far from the truth!
   PC Logic Analyzer                                                Page: 13


      5.2 Slowing it down

            PCLA samples at rates up to 500khz on some  computers,  however
         most small microccontrollers run at several megahertz,  and  often
         higher...

            If you are trying to resolve some hardware timing issue that is
         related to "race conditions" and other speed related issues,  then
         forget PCLA.  You need a fast hardware logic analyzer and a lot of
         patience!

            If however you are trying to debug a  straightforward  clocking
         or synchronization issue,  PCLA can be very  handy,  even  if  the
         target device is running faster than PCLA can sample.

         5.2.1 Software Solutions

               If the signals you are monitoring  are  being  generated  by
            software,  such as  "bit banging"  a clocked serial line for  a
            serially accessed peripheral,  then the solution  is  simple...
            Slow down the software! This can  usually  be  accomplished  by
            putting delay loops into the code at the  points  where  it  is
            toggleing the I/O lines.

               Once you get the process running slowly enough for  PCLA  to
            capture it, you can verify the logic, make fixes,  and once you
            get it working at the slower speed, just remove your loops, and
            watch it work at high speed!  (if not,  the problem  should  be
            fairly easy to track down as it is obviously timing related).

         5.2.2 Hardware solutions

               If the  signal  you  are  monitoring  is  generated  by  the
            hardware  (such  as  a  microprocessor  bus),  or  if   it   is
            impractical to slow down the software by code changes  (perhaps
            you do not have the source code),  then the next easiest  thing
            to do is to... Slow down the hardware!

               Practically  all  microprocessors  can  accept  an  external
            clock. In most cases, you just disconnect the crystal and drive
            one of it's connections with  the  external  clock.  Check  the
            datasheets for the microprocessor that you are using.

               Appendix B describes a small  programmable  clock  generator
            that can be used to produce an external clock from  4.0Mhz  all
            the way down to the audio range.  This device is easy to build,
            and is a very handy companion to PCLA.  Simply  connect  as  an
            external clock on your target system,  and you will be able  to
            easily adjust the clock speed to  exactly  suit  your  sampling
            requirements.
   PC Logic Analyzer                                                Page: 14


   6. File Formats

         The data saved by the F)ile function has the following format:

           2       - Configured Interval between samples (us)
           2       - Configured number of samples to capture
           1       - Current ending position in preview buffer(+1)
           1       - Trigger mask  value for A-E input lines
           1       - Trigger match value for A-E input lines
           1       - Trigger mask  value for 0-7 input lines
           1       - Trigger match value for 0-7 input lines
           256     - Preview buffer for A-E input lines *
           256     - Preview buffer for 0-7 input lines
           2 [A]   - Number of review entries
           1 [B]   - Review entry for A-E input lines *
           1 [B]   - Review entry for 0-7 input lines
               [B] entries repeat for [A] times (0=65536).

       * A-E entries are stored in the upper 5 bits of the byte, and
         the high bit (bit 7) is inverted.
   PC Logic Analyzer                                                Page: 15


   7. APPENDIX A - Modifying older Parallel Ports

         The original IBM Printer Adapter,  and many of  the  early  clones
      were very easy to modify to become bidirectional.  The output  driver
      for these cards is a 74LS347,  which has an -OE  line  (pin  1)  that
      allows it to be tristated,  effectivly removing it from the  circuit,
      leaving only the diagnostic "feedback"  registers,  which just happen
      to function exactly as a bidirectional port in input mode.

         It also happens,  that these ports use a 74LS174 hex latch for the
      control signals, and since there are only 5 control signals, there is
      an unused latch available.  If also happens that the  input  of  this
      unused latch is  already  connected  to  D5,  the  right  pin  for  a
      bidirectional control signal.  The output of this latch  (pin 15)  is
      not connected.

         All you need to do to make this type of port a bidirectional  port
      is to cut the trace from pin1 of the 74LS374  which  connects  it  to
      ground (always enabled), and connect that pin instead of pin15 of the
      74LS174 latch.  This causes the port to be configured  as  an  output
      when D5 of the control register is written with 0,  and as  an  input
      when D5 of the control register is written with 1.

      NOTE:  If you plan to use the parallel port only with PCLA,  and want
      to completely avoid the possibility of signal contention due  to  the
      output buffers being switched on,  you can simply disconnect pin1  of
      the 74LC374 from ground and connect it to +5v.. This will permanently
      remove the output driver from the circuit,  making the port an  input
      only port.
   PC Logic Analyzer                                                Page: 16


   8. APPENDIX B - A Programmable Clock Generator

         The  drawing  file   PCLOCK.DWG   contains   a   microcad   format
      programmable clock generator,  which can generate clock ranging  from
      4.00 Mhz down to the audio range.

         This device uses three 74LS163's,  two of them as  a  programmable
      divider,  and the last one as a flip-flop to  obtain  a  square  wave
      output,  and also provides divide by 2,  divide by 4 and divide by  8
      outputs, which can be used to further reduce the clock frequency,  or
      in cases where synchronized double/half clocks are required.

         The project can be built on a small  circuit  board,  and  can  be
      powered from the target system, or any available 5v supply.

         The following clock frequencies are available via the  DIP  switch
      setting:

       Mhz     Switch    Mhz     Switch    Mhz     Switch    Mhz     Switch
       ----------------  ----------------  ----------------  ----------------
       0.03125=00000000  0.03571=00000100  0.04167=00000010  0.05000=00000110
       0.03137=10000000  0.03587=10000100  0.04188=10000010  0.05031=10000110
       0.03150=01000000  0.03604=01000100  0.04211=01000010  0.05063=01000110
       0.03162=11000000  0.03620=11000100  0.04233=11000010  0.05096=11000110
       0.03175=00100000  0.03636=00100100  0.04255=00100010  0.05128=00100110
       0.03187=10100000  0.03653=10100100  0.04278=10100010  0.05161=10100110
       0.03200=01100000  0.03670=01100100  0.04301=01100010  0.05195=01100110
       0.03213=11100000  0.03687=11100100  0.04324=11100010  0.05229=11100110
       0.03226=00010000  0.03704=00010100  0.04348=00010010  0.05263=00010110
       0.03239=10010000  0.03721=10010100  0.04372=10010010  0.05298=10010110
       0.03252=01010000  0.03738=01010100  0.04396=01010010  0.05333=01010110
       0.03265=11010000  0.03756=11010100  0.04420=11010010  0.05369=11010110
       0.03279=00110000  0.03774=00110100  0.04444=00110010  0.05405=00110110
       0.03292=10110000  0.03791=10110100  0.04469=10110010  0.05442=10110110
       0.03306=01110000  0.03810=01110100  0.04494=01110010  0.05479=01110110
       0.03320=11110000  0.03828=11110100  0.04520=11110010  0.05517=11110110
       0.03333=00001000  0.03846=00001100  0.04545=00001010  0.05556=00001110
       0.03347=10001000  0.03865=10001100  0.04571=10001010  0.05594=10001110
       0.03361=01001000  0.03883=01001100  0.04598=01001010  0.05634=01001110
       0.03376=11001000  0.03902=11001100  0.04624=11001010  0.05674=11001110
       0.03390=00101000  0.03922=00101100  0.04651=00101010  0.05714=00101110
       0.03404=10101000  0.03941=10101100  0.04678=10101010  0.05755=10101110
       0.03419=01101000  0.03960=01101100  0.04706=01101010  0.05797=01101110
       0.03433=11101000  0.03980=11101100  0.04734=11101010  0.05839=11101110
       0.03448=00011000  0.04000=00011100  0.04762=00011010  0.05882=00011110
       0.03463=10011000  0.04020=10011100  0.04790=10011010  0.05926=10011110
       0.03478=01011000  0.04040=01011100  0.04819=01011010  0.05970=01011110
       0.03493=11011000  0.04061=11011100  0.04848=11011010  0.06015=11011110
       0.03509=00111000  0.04082=00111100  0.04878=00111010  0.06061=00111110
       0.03524=10111000  0.04103=10111100  0.04908=10111010  0.06107=10111110
       0.03540=01111000  0.04124=01111100  0.04938=01111010  0.06154=01111110
       0.03556=11111000  0.04145=11111100  0.04969=11111010  0.06202=11111110
   PC Logic Analyzer                                                Page: 17


       Mhz     Switch    Mhz     Switch    Mhz     Switch    Mhz     Switch
       ----------------  ----------------  ----------------  ----------------
       0.06250=00000001  0.08333=00000101  0.12500=00000011  0.25000=00000111
       0.06299=10000001  0.08421=10000101  0.12698=10000011  0.25806=10000111
       0.06349=01000001  0.08511=01000101  0.12903=01000011  0.26667=01000111
       0.06400=11000001  0.08602=11000101  0.13115=11000011  0.27586=11000111
       0.06452=00100001  0.08696=00100101  0.13333=00100011  0.28571=00100111
       0.06504=10100001  0.08791=10100101  0.13559=10100011  0.29630=10100111
       0.06557=01100001  0.08889=01100101  0.13793=01100011  0.30769=01100111
       0.06612=11100001  0.08989=11100101  0.14035=11100011  0.32000=11100111
       0.06667=00010001  0.09091=00010101  0.14286=00010011  0.33333=00010111
       0.06723=10010001  0.09195=10010101  0.14545=10010011  0.34783=10010111
       0.06780=01010001  0.09302=01010101  0.14815=01010011  0.36364=01010111
       0.06838=11010001  0.09412=11010101  0.15094=11010011  0.38095=11010111
       0.06897=00110001  0.09524=00110101  0.15385=00110011  0.40000=00110111
       0.06957=10110001  0.09639=10110101  0.15686=10110011  0.42105=10110111
       0.07018=01110001  0.09756=01110101  0.16000=01110011  0.44444=01110111
       0.07080=11110001  0.09877=11110101  0.16327=11110011  0.47059=11110111
       0.07143=00001001  0.10000=00001101  0.16667=00001011  0.50000=00001111
       0.07207=10001001  0.10127=10001101  0.17021=10001011  0.53333=10001111
       0.07273=01001001  0.10256=01001101  0.17391=01001011  0.57143=01001111
       0.07339=11001001  0.10390=11001101  0.17778=11001011  0.61538=11001111
       0.07407=00101001  0.10526=00101101  0.18182=00101011  0.66667=00101111
       0.07477=10101001  0.10667=10101101  0.18605=10101011  0.72727=10101111
       0.07547=01101001  0.10811=01101101  0.19048=01101011  0.80000=01101111
       0.07619=11101001  0.10959=11101101  0.19512=11101011  0.88889=11101111
       0.07692=00011001  0.11111=00011101  0.20000=00011011  1.00000=00011111
       0.07767=10011001  0.11268=10011101  0.20513=10011011  1.14286=10011111
       0.07843=01011001  0.11429=01011101  0.21053=01011011  1.33333=01011111
       0.07921=11011001  0.11594=11011101  0.21622=11011011  1.60000=11011111
       0.08000=00111001  0.11765=00111101  0.22222=00111011  2.00000=00111111
       0.08081=10111001  0.11940=10111101  0.22857=10111011  2.66667=10111111
       0.08163=01111001  0.12121=01111101  0.23529=01111011  4.00000=01111111
       0.08247=11111001  0.12308=11111101  0.24242=11111011  0 (DC) =11111111

         This device should be built with the packaged oscilator located in
      a socket,  allowing it to  be  changed  to  obtain  even  more  clock
      frequencies. Just scale the above chart accordingly.
   PC Logic Analyzer                                                Page: 18


   9. APPENDIX C - Making a clean boot disk

         To make a DOS boot disk,  you need a DOS or Windows9x system.  You
      cannot make a DOS boot disk from a WindowsNT system (although you can
      still boot the disk).

         If you are running Windows95 OSR2 or later, and need to be able to
      access your hard drive from the booted floppy,  then you should  make
      your boot disk from the Windows DOS prompt.

      The steps in making a boot disk are:

       1) Insert a blank floppy disk into your A: drive.
          ANY data already on this disk will be lost!

       2) Get to the DOS prompt.
          If you are running Windows3.1, exit to the DOS prompt.
          If you are running Windows9x, activate the "MS-DOS Prompt"
          item on the start menu/Programs.

       3) At the DOS prompt, enter the command: FORMAT A: /S /U
           /S tells FORMAT to put a bootable SYSTEM on the disk
           /U tells format to do a complete (uncondional) format
        * If you are running an older version of DOS, FORMAT may not
          accept the '/U' option, in which case, just leave it off,
          as older DOS versions always do an unconditional format.

       4) Position to the directory where PCLA is installed.
          Assuming that you installed to the default: C:\PCLA,
          use the command: CD C:\PCLA

       5) Copy the PCLA.COM program onto the floppy disk:
          use the command: COPY C:PCLA.COM A:

       6) If you want any other commands on your disk, copy them on
          at this time. DOS usually stores it commands in "C:\DOS",
          while Windows9x puts them in "C:\WINDOWS\COMMAND".
          If you don't know where a particular command is located, try
          typing 'PATH'. This will show you all of the directories
          where the system searches for commands. You may have to go
          through them one by one to find the command.

      Your BOOT disk is now complete.  You should be able to shut down your
      computer, insert the FLOPPY disk into your A: drive,  and reboot into
      a clean copy of DOS.  If you are prompted for the TIME and DATE  when
      the system boots,  just press ENTER.  You will receive a DOS  prompt,
      and you can run PCLA,  or any other commands that you copied onto the
      disk.
   PC Logic Analyzer                                                Page: 19


      If your system boots from the hard drive,  even with the BOOT disk in
      drive A:,  then the most likely cause is that  your  system  BIOS  is
      configured to boot directly from the hard drive.

      You may have to consult your system documentation to change the  boot
      type, however generally, you will have to:

       1) Watch the computer startup screen closely when it is first
          turned on... Usually there will be a prompt to press a certain
          key to enter the BIOS setup/configuration. Often this key is
          DEL, but sometimes it is something else.

       2) When prompted, press the KEY. This should get you into the
          BIOS setup screens.

       3) Look for an item with a name something like "BIOS features" or
          "BIOS options" and select it.

       4) Look for any options which indicate how the system boots. It
          will be called "System BOOT", "System BOOT sequence", "Boot
          order" or something similar. It will most likely be set to
          some option in which C appears before A, such as "C only",
          "C,A", "CDROM,C,A", "C then A" or something similar.

       5) Find the keys to change the options, and change the BOOT option
          to "A,C" or another suitable option in which "A" appears before
          "C". Make sure that "C" is mentioned in the option, or else you
          system may not boot from the hard drive at all (you can always
          come back here and fix it if this happens).
          DO NOT change any other options in the BIOS setup screens!

       6) Exit the "BIOS options" screen, and find the key to "Save and
          Exit Setup" (or something similar).

      Once you have saved the new settings,  your system should  BOOT  from
      the floppy disk if one is present in the A:  drive when the system is
      turned on or reset.
